It is well known for memory devices to latch address, data and command information before they are processed to a memory core, i.e. memory banks, blocks, or other type of storage areas. However, a problem with such latching is that the separate clock, address data, and control paths often have differing lengths and inherent delays. For example, FIG. 2 illustrates the an exemplary address signal line a clock signal XCLK used to latch in address data bit at latch 220. It is important that the address at the output of address buffer 208 be valid when the clock causes the transistor 216 to turn on and latch in the address data.
FIG. 1 shows the two important portions of the clock signal XCLK which are the setup time tSETUP which occurs right before the transistor 216 is turned on, and the hold time tHOLD which is the time during which the transistor 216 is on. The address, command, and data information on their associated signal lines has to be present and stable during the hold time tHOLD, which allows for a small amount of variation in the shape of the rising edge of the clock signal. The rising edge of the XCLK signal should ideally occur during the middle of the time address, command, or data signal is present and available for latching.
Referring back to FIG. 2, the clock XCLK and ADDRESS signal lines typically have different signal propagation delay times. This is because the clock signal goes through a buffer 204 having a delay td1, a clock regenerator device 212 having an additional delay td2, and then the inherent delay td3 of the clock line before arriving at transistor 216. The clock regenerator 212 reduces noise and instability in a clock signal, but has the disadvantage of introducing delay in doing so. The transistor 216 controls the loading of the latch 220. The address lines, only one of which is shown in FIG. 2 (as well as the data and command signal lines) only goes through the input buffer 208, which imposes the delay tIB which also includes a delay between buffer 208 and transistor 216. Ideally, td1, td2, and td3 should equal tIB. Unfortunately, this is seldom true, so that the signals on the address, command, and data lines arrive at different times than the clock signals, with the clock signal generally lagging behind the address, data, and control signals. In acute situations these time differences produce errors in the latching of the addresses, commands, and data.
One known way of compensating for the differing signal delays includes adding delay in the fastest signal path to balance against the slowest signal path. Thus, FIG. 3 shows a conventional approach where an additional delay 316 is positioned between the input buffer 208 and transistor 216 in the address line of FIG. 2. The delay 316 can be achieved with serial inverters (FIG. 4), or serial inverters with a capacitor 512 located between them (FIG. 5). The added delays adjust the timing of an address, data or control signal in a measurable, predictable way. However, it is desired to get the address, command, and data signals to the memory core as quickly as possible. Introducing delay at the input buffer, though necessary for proper signal latching synchronization, reduces the overall speed of the memory device. Also, once the delay 316 is introduced into a circuit there is no way to remove or make adjustments to it.